Exemplary embodiments relate to a semiconductor memory device and a method of operating the same and, more particularly, to a nonvolatile memory device and a method of operating the same.
A NAND flash memory device is a representative nonvolatile memory device. The memory cell array of the NAND flash memory device includes a plurality of memory blocks. Each of the memory blocks includes a plurality of memory strings coupled between bit lines and a common source line. Each of the memory strings includes a drain select transistor, memory cells, and a source select transistor coupled in series between each bit line and the common source line. The gates of the drain select transistors are coupled to a drain select line, the control gates of the memory cells are coupled to respective word lines, and the gates of the source select transistors are coupled to a source select line.
In order to store data in the memory cells, a program operation is performed. The program operation is performed on memory cells from memory cells, coupled to a word line adjacent to the source select line within one memory block, to memory cells coupled to a word line adjacent to the drain select line. Furthermore, the program operation for even pages, including even-numbered ones of memory cells coupled to a selected word line, is first performed, and a program operation for odd pages, including odd-numbered ones of the memory cells coupled to the selected word line is then performed.
With the degree of integration increasing, the interval between memory cells is narrowed. Accordingly, a program interference phenomenon is generated in memory cells, coupled to a word line adjacent to a selected word line or included in a page adjacent to a selected page, during a program operation. Consequently, the threshold voltages of the memory cells are shifted.
Since the even page program operation is performed earlier than the odd page program operation, the threshold voltages of memory cells included in the even pages are relatively greatly shifted owing to the program interference phenomenon. Accordingly, a threshold voltage distribution of the memory cells may be widened, and an error may occur in an operation of reading data.